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// SIMULATION · REQUIRED
↑
Drop .vcd or .zip, or click to upload
Value Change Dump from any simulator
✕ REMOVE
// FPGA / SECOND CAPTURE · OPTIONAL
↑
Drop .vcd to compare against simulation
Unlocks the Sim vs FPGA comparison
✕ REMOVE
ANALYZE
PREPARING...
01 //
02 //
03 //
// MULTIPLE VCD FILES FOUND
The zip contains more than one VCD. Choose which file is the simulation and which (optional) is the second capture.
SIMULATION
SECOND CAPTURE
CANCEL
CONFIRM
VCD
Insight
// NO FILE LOADED
SYSTEM READY
← UPLOAD NEW FILE
// ANALYSIS_MODULES
Select a module to begin analysis
01
Waveform Viewer
Interactive waveforms with zoom, cursors and the signal inspector
VIEWER
→
02
Signal Overview
All signals — name, scope, bit width and detected role
SIGNALS
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03
Signal Health
Activity, X / Z states, stuck signals and glitches — reset aware
HEALTH
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04
Transactions
Handshakes, latency and wait cycles detected from the waveform
TRANSACTIONS
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05
Rules & Checks
Build rules and get PASS / FAIL with exact timestamps
RULES
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06
Sim vs FPGA
Compare two captures cycle by cycle and find the first mismatch
COMPARE
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07
Final Verdict
PASS / WARNING / FAIL with reasons and the full run story table
VERDICT
→
08
Export Report
Download the full analysis as a formatted report
EXPORT
↓
← BACK TO MODULES